Bump Heights ≤ 130um
SFC – Bump on I/O
Our Standard Flip Chip (SFC) process, formerly known as the Flex-on-Cap (or FoC) process, was originally developed in the mid-1960’s by Delco for use in the automotive industry. Today, the process has unsurpassed industry track record with 40 years and millions of bumped wafers behind it. This is the process to use when you need to place small bumps (less than 130μm in height) directly on the die I/O. Pitch capabilities in this process are typically 150μm or greater for a full array I/O or peripheral I/O design.
Typically, the number of bumps per die ranges from 4 to 6000. The SFC process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal constraints of an electroplating process, a wide range of multi-metal solder alloys tailored to your application (such as Sn/Ag/Cu alloys) are available. As with all flip chip die processed with small bumps, these die will require the use of underfilling during packaging in order to achieve acceptable reliability.
To take advantage of this process flow, the device must meet some minimum I/O pad requirements (described in section 3.1.2 of the Design Guide). If the device does not meet these minimum I/O pad requirements, refer to section 3.2, which outlines SFC Repassivation alternatives. If you are looking for bump heights greater than 130μm, refer to sections 3.5 and 3.6, and consider the UltraCSP and/or Spheron WLCSP flows.
Standard Flip Chip-Bump on I/O Process Summary
The SFC-Bump on I/O process supports fine pitch flip chip applications to pitches well below 100μm. Below is an outline of the flow:
SFC – Repassivation (Spheron™ or BCB)
Our SFC-Repassivation process flows are similar to the SFC-Bump on I/O process, but support bumping applications that do not meet all of the I/O final metal pad and passivation opening requirements of SFC-Bump on I/O. In this process, a stress relieving layer of either Benzocyclobutene (BCB) or Spheron™ (an FCI proprietary high performance dielectric repassivation layer) is deposited on the die before bumping. The repassivation layer corrects for the issue of the I/O passivation opening being too small or too large for a standard flip chip bump. It also corrects for the issue of the I/O final metal pad being too small for a standard flip chip bump. The repassivation dielectric layer also planarizes the device surface and gives the bump structure additional strength and robustness.
As with SFC-Bump on I/O, SFC-Repassivation is designed for small bumps (less than 130μm) placed directly on the die I/O. Pitch capabilities in this process are typically 150μm or greater for full array I/O or peripheral I/O design. The number of bumps per die typically can range from 4 to 6000. The SFC-Repassivation process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal constraints of an electroplated solder process, multi-metal alloy (including Sn/Ag/Cu) options are readily available. As with all die processed with small bumps, die bumped with the SFC-Repassivation process will require the use of underfill during packaging.
If your device contains bumps that will not be placed directly on the I/O, take a look at section 3.3 in the Design Guide, which describes the SFC-Redistribution flow. If you are looking for bump heights greater than 160μm, take a look at section 3.5 and 3.6 in the Design Guide, which covers the Spheron and UltraCSP WLCSP flows – the industry’s standards in Wafer Level Chip Scale Packaging solutions.
SFC-Repassivation Process Summary
The SFC-Repassivation process requires relatively few process steps to complete the flow. Below is an outline of the process flow for BCB or Spheron polymer (none of the drawings are to scale):
SFC – Redistribution (Spheron™ or BCB)
On some die, the I/O are not located where you need to have the bumps. This is especially true when you take a die originally designed for wire bond packaging applications and need to convert it to be flip chip compatible. The SFC-Redistribution Line (or RDL) process adds “redistribution metallization” (often called “runners’ or “traces”) that let you re-route the signal path from the die peripheral I/O to an area array of new bump locations, often with significant loosening of effective bump pitches.
Although a single RDL layer is most commonly used today, FCI has successfully supported more complex SFC-RDL applications involving up to 3 metal layers. Although FCI’s metallization schemes have historically involved subtractive, sputtered metal RDL and UBM options, more recently, FCI has also added semi-additive electroplated Cu based options to its product lineup. Redistribution SFC bumping flows are intended to produce bumps of less than 130μm in height, although the typical bump height is -100um.
Typical pitch capabilities in this process are 70μm or greater. RDL runners using subtractive sputtered metallization schemes are allowed a minimum of 20um wide lines and 22um wide spaces. For finer pitch, higher aspect ratio RDL requirements, including On Chip Inductor applications, FlipChip also has available semi-additive Cu electroplated metallization schemes which allow a minimum of 8um wide lines and 10um wide spaces if needed. Since the SFC process is not limited to the bi-metal constraints of an electroplated solder process, multi-metal alloys (including Sn/Ag/Cu) are readily available. As with all die processed with small bumps, these die will require the use of underfill during packaging.
BCB SFC-Redistribution Process Summary
The BCB SFC-RDL process requires more process steps than the SFC-Bump on I/O or the SFCRepassivation flows. Below is an outline of the BCB SFC-Redistribution subtractive, sputtered metallization process sequence with its characteristic Bump on Nitride construction (none of the drawings are to scale):
Spheron™ SFC-Redistribution Process Summary
The Spheron SFC-RDL process also requires more process steps than the SFC-Bump on I/O or the SFC-Repassivation flows. Below is an outline of the Spheron SFC-Redistribution subtractive, sputtered metallization process sequence with its characteristic Bump on Polymer construction (none of the drawings are to scale):
Cu Pillar Bump - Repassivation (Spheron™)
As the industry has continued to drive flip chip applications to bump pitches of 150μm and below, significant assembly challenges related to underfilling flip chip assemblies on laminate substrates has arisen due to associated decreases in chip stand-offs. Cu Pillar Flip Chip bumping has emerged as an attractive option both for high end computing and more recently for wireless flip chip, System in Package (SiP) applications, where the predictable stand-off of a copper post can effectively minimize assembly and underfilling problems.
Since FCI is a dominant force in bumping for the wireless electronics space, FCI has developed and qualified a robust Cu Pillar Bump Repassivation technology for use on silicon and GaAs flip chip applications. FCI’s Standard Pillar Bump technology targets applications of 100 micron pitch and greater, while the more recent NANOPillarTM Bump alternative supports ultra-fine pitch flip chip applications down to 35 micron pitch. NANOPillar Bumps target flip chip on silicon applications which are becoming increasingly common in an assortment of 3D packaging schemes.
In order to ensure successful deployment of this product offering, FCI opted to take a Cu Pillar Bump license from APS, a well recognized Singaporean technology company. Unlike the rest of the industry however, FCI’s Cu Pillar Bump offering involves solder capping of plated Cu posts of FlipChip International, LLC Bumping Design Guide www.flipchip.com Page 15 definable heights, using a minor variant of its widely accepted, proprietary SFC printed bump process. This flow uses premixed solder paste for formation of the solder cap and as a result is not limited to the bi-metal constraints of an all electroplating Cu Pillar Bump technology.
Multi-metal alloys (including a broad assortment of Sn/Ag/Cu alloys) can be selected to match the particular requirements of specific applications. The generous die stand-offs that result from Cu Pillar Bumps enable ease of assembly, particularly at underfill. In the case of Flip Chip SiP applications, the elimination of underfill process steps and dimensional design keep outs enabling vacuum-assisted transfer molding for simultaneous die underfilling and package overmolding is enabled.
In this flip chip bumping alternative, a dielectric repassivation layer of either Benzocyclobutene (or BCB) or Spheron can be selected as a localized stress reliever in the bump location on the die before bumping. As with SFC-Bump on I/O and SFC-Repassivation, FCI’s Cu Pillar Bump - Repassivation offering is designed for small flip chip bumping applications (less than 130μm in diameter) placed directly on the die I/O. FCI’s Cu Pillar Bump can also be readily incorporated with FCI’s plated Cu RDL options should it be required.
Cu Pillar Bump - Repassivation Process Summary
The Cu Pillar Bump - Repassivation process flows were designed to have significant commonality with FCI’s other bumping options. Below is an outline of a generic Cu Pillar Bump process flow (none of the drawings are to scale):
EliteFC™ – Electroless Ni/Au
EliteFC is a Flip Chip smaller sized bumping technology that uses the low cost E-less Ni/Au UBM. Typical bump heights are 70μm - 130μm depending on bump pitch and configuration. EliteFC can often be used as a lower cost alternative to traditional Standard Flip Chip.
Devices that are to be bumped using any of the Elite processes need to have some special requirements met. These requirements are described in Section 4.3.12 of the Design Guide.
EliteFC™ – Process Flow
