Bump Heights ≥ 160um
Spheron™ WLCSP – Bump on I/O and
Spheron™ WLCSP – Redistribution
FlipChip’s Flagship Spheron™ WLCSP technology utilizes a proprietary dielectric material, which offers improved electrical performance and reliability over other polymer repassivation options. In addition to its advanced dielectric material, the Spheron WLCSP™ product family incorporates a growing number of subtractive sputtering and semi-additive electroplated Cu based metallization options targeting specific customer needs. For example, some of the Spheron WLCSP product breadth over the past few years has been developed in response to the evolving board level requirements of portable handheld products.
Benefits of Spheron WLCSP options include: improved electrical performance, reduced capacitive coupling between UBM/Solder and the underlying IC circuitry, improved solder joint reliability, significant improvement in thermal cycling performance due to die planarization/polymer film characteristics, and elimination of incoming wafer topology issues. In addition, this planarizing polymer film ensures proper UBM step coverage, even over non-planarized devices. Spheron is compatible with silicon nitride and silicon dioxide passivations.
Spheron WLCSPs use pre-formed solder spheres of 200μm to 500μm in diameter to routinely bump device pitches ranging from 0.35 to 0.8 mm pitch and reflowed for final bump heights of 160μm to 400μm. In this process, the bumps can be placed directly on the device I/O’s or the bump location may be redistributed to a more desirable die location. For WLCSPs, the number of bumps per die is typically in the range of 4 to 100 with upper array size limitations being based primarily on end-user board level reliability requirements rather than any bumping constraints. Die bumped with Spheron WLCSP typically do not require underfill. Spheron WLCSPs have been demonstrated to be JEDEC Level 1 compliant.
Spheron WLP™ Redistribution – Standard Process Flow
The Spheron WLP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. An example of the subtractive sputtered metallization redistributed process options available is shown (none of the drawings are to scale).
Electroplated Cu Spheron™ WLCSP – Redistribution
Spheron WLCSP™ Electroplated Cu Redistribution Process Flow
The Spheron WLCSP Electroplated Cu process may be used to bump directly on I/O or may be used to redistribute bumps to a more appropriate die location. A representative flow of FCI’s Semi-Additive Electroplated Cu RDL process is outlined below (none of the drawings are to scale).
UltraCSP® WLCSP – Bump on I/O and
UltraCSP® WLCSP – Redistributed
UltraCSP® is our patented Wafer Level Chip Scale Package (or WLCSP) process. Since its introduction in 1998, UltraCSP has become the industry’s standard for WLCSP. Bump heights for the process range from 160μm to 400μm depending on pitch. In this process, pre-formed solder spheres of 200μm to 500μm in diameter are placed on the wafer and reflowed. The bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 to 100. Die bumped with UltraCSP do not require underfill until the bump array reaches the 6x6 to 7x7 size. For larger bump arrays underfill may be needed depending on the reliability requirements of the particular application. The lack of underfill makes it easy to migrate TSOP or QFP to UltraCSP. Ultra CSP is classified as a JEDEC Level 1 compliant packaging option.
UltraCSP® Process Summary
The UltraCSP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. Both processes are summarized below (none of the drawings are to scale).
UltraCSP® Bump on I/O - Process Flow
UltraCSP® Redistributed - Process Flow
EliteCSP™ – Electroless Ni/Au
EliteCSP is a Wafer Level-Chip Scale Package (WL-CSP) that uses the E-less UBM structure. As with UltraCSP, pre-formed solder spheres of 200μm to 500μm are placed on the wafer and reflowed for final bump heights of 160μm to 400μm. Typical applications for EliteCSP include very cost sensitive as well as high power / high temperature devices.
Devices that are to be bumped using any of the Elite processes need to have some special requirements met. These requirements are described in Section 4.3.12 of the Design Guide.
EliteCSP™ – Process Flow
